Test RWC+ctrlisb+dsb.st

ARM RWC+ctrlisb+dsb.st
"Rfe DpCtrlIsbdR Fre DSB.STdWR Fre"
Cycle=Rfe DpCtrlIsbdR Fre DSB.STdWR Fre
Prefetch=0:x=T,1:x=F,1:y=T,2:y=F,2:x=T
Com=Rf Fr Fr
Orig=Rfe DpCtrlIsbdR Fre DSB.STdWR Fre
{
%x0=x;
%x1=x; %y1=y;
%y2=y; %x2=x;
}
 P0           | P1           | P2           ;
 MOV R0,#1    | LDR R0,[%x1] | MOV R0,#1    ;
 STR R0,[%x0] | CMP R0,R0    | STR R0,[%y2] ;
              | BNE LC00     | DSB ST       ;
              | LC00:        | LDR R1,[%x2] ;
              | ISB          |              ;
              | LDR R1,[%y1] |              ;
exists (1:R0=1 /\ 1:R1=0 /\ 2:R1=0)