AArch64 WRW+WR+poxxs+X "RfeXX PodRWXX WseXX PodWRXX FreXX" Cycle=RfeXX PodRWXX WseXX PodWRXX FreXX Relax= Safe=PodWR PodRW RfeXX FreXX WseXX Prefetch=1:x=F,1:y=W,2:y=F,2:x=T Com=Rf Ws Fr Orig=RfeXX PodRWXX WseXX PodWRXX FreXX { ok=1; 0:X0=x; 0:X5=ok; 1:X0=x; 1:X3=y; 1:X7=ok; 2:X0=y; 2:X4=x; 2:X7=ok; } P0 | P1 | P2 ; MOV W1,#1 | LDXR W1,[X0] | MOV W1,#2 ; LDXR W2,[X0] | STXR W2,W1,[X0] | LDXR W2,[X0] ; STXR W3,W1,[X0] | CBNZ W2,Fail1 | STXR W3,W1,[X0] ; CBNZ W3,Fail0 | MOV W4,#1 | CBNZ W3,Fail2 ; B Exit0 | LDXR W5,[X3] | LDXR W5,[X4] ; Fail0: | STXR W2,W4,[X3] | STXR W3,W5,[X4] ; MOV W4,#0 | CBNZ W2,Fail1 | CBNZ W3,Fail2 ; STR W4,[X5] | B Exit1 | B Exit2 ; Exit0: | Fail1: | Fail2: ; | MOV W6,#0 | MOV W6,#0 ; | STR W6,[X7] | STR W6,[X7] ; | Exit1: | Exit2: ; Observed y=2; x=1; ok=1; 2:X5=0; 2:X2=1; 1:X5=0; 1:X1=1; 0:X2=0; and y=2; x=1; ok=0; 2:X5=0; 2:X2=1; 1:X5=0; 1:X1=1; 0:X2=0;