Test S+dmb.sts

AArch64 S+dmb.sts
"DMB.STdWW Rfe DMB.STdRW Wse"
Cycle=Rfe DMB.STdRW Wse DMB.STdWW
Relax=
Safe=Rfe Wse DMB.STdWW DMB.STdRW
Prefetch=0:x=F,0:y=W,1:y=F,1:x=W
Com=Rf Ws
Orig=DMB.STdWW Rfe DMB.STdRW Wse
{
0:X1=x; 0:X3=y;
1:X1=y; 1:X3=x;
}
 P0          | P1          ;
 MOV W0,#2   | LDR W0,[X1] ;
 STR W0,[X1] | DMB ST      ;
 DMB ST      | MOV W2,#1   ;
 MOV W2,#1   | STR W2,[X3] ;
 STR W2,[X3] |             ;
exists
(x=2 /\ 1:X0=1)